1. Technical Field
Various embodiments relate to a semiconductor circuit, and more particularly, to a digital counter.
2. Related Art
A digital counter is used in various technical fields. For example, the digital counter may be used in a sensing circuit for correlated double sampling (CDS) to improve the uniformity of CMOS image sensors.
At this time, CDS may be divided into analog CDS and digital CDS (DDS). Since the DDS has higher speed and precision than the analog CDS, the DDS is more frequently used.
However, the DDS requires a digital counter for each channel. For example, when a 10-bit sensing circuit is constructed, 10 digital counters are used for each channel, and several thousand digital counters are used as a whole.
When such a large number of digital counters are used for the DDS, power consumption inevitably increases. Thus, the power consumption of the digital counters needs to be reduced.
FIG. 1 is a circuit diagram of a conventional digital counter 10.
An N-bit digital counter may include N flip-flops. FIG. 1 illustrates a conventional four-bit digital counter, and the four-bit digital counter includes first to fourth flip-flops DFF0 to DFF3.
Each of the first to fourth flip-flops DFF0 to DFF3 has an inverting output terminal Qb coupled to an input terminal D thereof.
The first flip-flop DFF0 has a clock terminal configured to receive a clock signal CLK.
Each of the second to fourth flip-flops DFF1 to DFF3 have a clock terminal coupled to the inverting output terminal Qb of the previous flip-flop.
The first to fourth flip-flops DFF0 to DFF3 output signals of the respective output terminals Q as count signals D<0:3>.
FIG. 2 is a circuit diagram illustrating the internal configuration of the first flip-flop DFF0 of FIG. 1.
Referring to FIG. 2, the first flip-flop DFF0 includes a first latch LT1 and a second latch LT2.
The first latch LT1 is configured to latch a signal inputted through the input terminal D, maintain a node N1 to the level of the signal inputted through the input terminal D, and include a plurality of transmission gates and a plurality of inverters.
The second latch LT2 is configured to latch the level of the node N1, maintain the levels of the output terminal Q and the inverting output terminal Qb, and include a plurality of transmission gates and a plurality of inverters.
At this time, the second to fourth flip-flops DFF1 to DFF3 are configured in the same manner as the first flip-flop DFF0.
FIG. 3 is an operation timing diagram of FIG. 1.
Referring to FIG. 3, the first and second latches LT1 and LT2 of the first to fourth flip-flops DFF0 to DFF3 in the conventional digital counter 10 are sequentially operated according to the clock signal CLK, thereby increasing the logic values of the count signals D<0:3>.
While the conventional digital counter 10 performs the operation of increasing the logic values of the count signals D<0:3> as illustrated in FIG. 3, output signals of the first and second latches LT1 and LT2 of the first to fourth flip-flops DFF0 to DFF3 may be toggled. The toggling serves as a main factor of power consumption.